The ThunderX2 product family is Cavium’s 2nd generation 64-bit ARMv8-A server processor SoCs for High Performance Computing in the Data Center and cloud applications. With fully out of order high performance custom cores supporting single and dual socket configurations, ThunderX2 is optimized to drive highest computational performance delivering outstanding memory bandwidth and memory capacity. The ThunderX2 processor family is fully compliant with ARMv8-A architecture specifications as well as ARM’s SBSA and SBBR standards and is widely supported by industry leading OS, Hypervisor and SW tool and application vendors.
The new Mont-Blanc prototype will be built by Atos, the coordinator of phase 3 of Mont-Blanc, using its Bull expertise and products. The platform will leverage the infrastructure of the Bull sequana pre-exascale supercomputer range for network, management, cooling, and power. Atos and Cavium signed an agreement to collaborate to develop this new platform, thus making Mont-Blanc an Alpha-site for ThunderX2.
"ThunderX2 is a server-class chip designed for high compute performance. With the adoption of this new generation of power- and performance-efficient processors, we are entering a new and exciting dimension of the Mont-Blanc project. This already gives us a glimpse of what a European exascale-class HPC platform could be in the near future." says Etienne Walter, coordinator of phase 3 of the Mont-Blanc project.
“As the race to Exascale intensifies, we are pleased to be the vendor of choice to partner with Atos to deliver Mont-Blanc platform” said Rishi Chugh, Director of Marketing, Data Center Processor Group at Cavium. “ThunderX2 builds on established architecture and ecosystem of ThunderX delivering performance competitive with next generation of incumbent processors”.
About the Mont-Blanc project”
The current third phase of the Mont-Blanc project continues to take a holistic approach, encompassing hardware, operating system and tools, and applications, with the following targets:
• Defining the architecture of an Exascale-class compute node based on the ARM architecture, and capable of being manufactured at industrial scale;
• Assessing the available options for maximum compute efficiency;
• Developing the matching software ecosystem to pave the way for market acceptance of ARM solutions.
The project is run by a European consortium that includes:
• Industrial hardware/software technology providers: Atos, using its expertise in supercomputing & Big data following the acquisition of Bull (coordinator - France); ARM, the world leader in embedded high-performance processors (United Kingdom); and AVL, the world's largest independent company for the development, simulation and testing technology of powertrains (Austria);
• Academic/research HPC centres: Barcelona Supercomputing Centre (Spain); Swiss Federal Institute of Technology in Zurich (Switzerland); CNRS (CNRS/LIRMM - France); University of Stuttgart (HLRS -Germany); University of Cantabria (Spain); University of Graz (Austria); University of Versailles Saint Quentin (France).
This project has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 671697.
